100 Gbps CMOS Transceiver for Multilane Optical Backplane System with a 1.3 cm Square Footprint

Thursday, 22 September, 2011
11:15 -- 13:00, Room B
Th.12.B • Devices For Signal Processing
 

Th.12.B.5 • 12:30 (Invited)

100-GBPS CMOS TRANSCEIVER FOR MULTILANE OPTICAL BACKPLANE SYSTEM WITH 1.3-CM2 FOOTPRINT

Takashi Takemoto1,5, Fumio Yuki1,5, Hiroki Yamashita1,5, Shinji Tsuji1,5, Yong Lee1,5, Koichiro Adachi1,5, Kazunori Shinoda1,5, Yasunobu Matsuoka1,5, Kenji Kogo1,5, Shinji Nishimura2,5, Masaaki Nido3,5, Masahiko Namiwaka3,5, Taro Kaneko3,5, Takara Sugimoto3,5, Kazuhiko Kurata4,5; 1Central Research Laboratory, Hitachi Ltd., Japan; 2Central Research Laboratory, Hitachi Ltd., Japan; 3Fiber Optics Devices Division, NEC Corp., Japan; 4Green Innovation Research Lab., NEC Corp., Japan; 5PETRA, Japan.
A compact 25-Gbps × 4-channel optical transceiver has been fabricated for optical backplane systems. Power consumption was as low as 20 mW/Gbps. A transmission experiment was successfully conducted at 25 Gbps.
 


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